RegViz: Visualize GTDNSR Bitfield

Renesas Electronics /R7FA4M3AF /GPT320 /GTDNSR

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Interpret as GTDNSR

DSELCG=0, DSELCH=0, DSCBFAL=0, DSELCD=0, DSGTRGCF=0, DSGTRGBR=0, DSELCE=0, DSGTRGBF=0, DSELCF=0, DSCBRAL=0, DSELCB=0, DSCAFBL=0, DSCBFAH=0, DSGTRGAR=0, DSCARBH=0, DSGTRGDR=0, DSCARBL=0, DSGTRGDF=0, DSGTRGCR=0, DSGTRGAF=0, DSCBRAH=0, DSELCA=0, DSELCC=0, DSCAFBH=0

Description

General PWM Timer Down Count Source Select Register

Fields

DSGTRGAR	GTETRGA Pin Rising Input Source Counter Count Down Enable 0 (0): Counter count down disabled on the rising edge of GTETRGA input 1 (1): Counter count down enabled on the rising edge of GTETRGA input
DSGTRGAF	GTETRGA Pin Falling Input Source Counter Count Down Enable 0 (0): Counter count down disabled on the falling edge of GTETRGA input 1 (1): Counter count down enabled on the falling edge of GTETRGA input
DSGTRGBR	GTETRGB Pin Rising Input Source Counter Count Down Enable 0 (0): Counter count down disabled on the rising edge of GTETRGB input 1 (1): Counter count down enabled on the rising edge of GTETRGB input
DSGTRGBF	GTETRGB Pin Falling Input Source Counter Count Down Enable 0 (0): Counter count down disabled on the falling edge of GTETRGB input 1 (1): Counter count down enabled on the falling edge of GTETRGB input
DSGTRGCR	GTETRGC Pin Rising Input Source Counter Count Down Enable 0 (0): Counter count down disabled on the rising edge of GTETRGC input 1 (1): Counter count down enabled on the rising edge of GTETRGC input
DSGTRGCF	GTETRGC Pin Falling Input Source Counter Count Down Enable 0 (0): Counter count down disabled on the falling edge of GTETRGC input 1 (1): Counter count down enabled on the falling edge of GTETRGC input
DSGTRGDR	GTETRGD Pin Rising Input Source Counter Count Down Enable 0 (0): Counter count down disabled on the rising edge of GTETRGD input 1 (1): Counter count down enabled on the rising edge of GTETRGD input
DSGTRGDF	GTETRGD Pin Falling Input Source Counter Count Down Enable 0 (0): Counter count down disabled on the falling edge of GTETRGD input 1 (1): Counter count down enabled on the falling edge of GTETRGD input
DSCARBL	GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Count Down Enable 0 (0): Counter count down disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 1 (1): Counter count down enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0
DSCARBH	GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Count Down Enable 0 (0): Counter count down disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 1 (1): Counter count down enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1
DSCAFBL	GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Count Down Enable 0 (0): Counter count down disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 1 (1): Counter count down enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0
DSCAFBH	GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Count Down Enable 0 (0): Counter count down disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 1 (1): Counter count down enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1
DSCBRAL	GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Count Down Enable 0 (0): Counter count down disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 1 (1): Counter count down enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0
DSCBRAH	GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Count Down Enable 0 (0): Counter count down disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 1 (1): Counter count down enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1
DSCBFAL	GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Count Down Enable 0 (0): Counter count down disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 1 (1): Counter count down enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0
DSCBFAH	GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Count Down Enable 0 (0): Counter count down disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 1 (1): Counter count down enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1
DSELCA	ELC_GPTA Event Source Counter Count Down Enable 0 (0): Counter count down disabled at the ELC_GPTA input 1 (1): Counter count down enabled at the ELC_GPTA input
DSELCB	ELC_GPTB Event Source Counter Count Down Enable 0 (0): Counter count down disabled at the ELC_GPTB input 1 (1): Counter count down enabled at the ELC_GPTB input
DSELCC	ELC_GPTC Event Source Counter Count Down Enable 0 (0): Counter count down disabled at the ELC_GPTC input 1 (1): Counter count down enabled at the ELC_GPTC input
DSELCD	ELC_GPTD Event Source Counter Count Down Enable 0 (0): Counter count down disabled at the ELC_GPTD input 1 (1): Counter count down enabled at the ELC_GPTD input
DSELCE	ELC_GPTE Event Source Counter Count Down Enable 0 (0): Counter count down disabled at the ELC_GPTE input 1 (1): Counter count down enabled at the ELC_GPTE input
DSELCF	ELC_GPTF Event Source Counter Count Down Enable 0 (0): Counter count down disabled at the ELC_GPTF input 1 (1): Counter count down enabled at the ELC_GPTF input
DSELCG	ELC_GPTG Event Source Counter Count Down Enable 0 (0): Counter count down disabled at the ELC_GPTG input 1 (1): Counter count down enabled at the ELC_GPTG input
DSELCH	ELC_GPTF Event Source Counter Count Down Enable 0 (0): Counter count down disabled at the ELC_GPTF input 1 (1): Counter count down enabled at the ELC_GPTF input

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